Duty cycle distortion (DCD) sampling in a low-swing transmitter
US11894847B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Aug 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.