Timing precision maintenance with reduced power during system sleep
US11895588B2 · kind B2 · utility
0Cited by
10References
16Claims
0Family size
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Key dates
| Filing date | Jul 26, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Feb 7, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide systems and methods for maintaining timing precision in different operating modes of a device (e.g., a wireless node). A timing circuit may switch clock signals between two different modes (e.g., high power and low power) while preserving timing precision. In a high-power mode, the timing circuit may provide a high frequency clock signal, and in a lower-power mode, it may provide a low frequency clock signal. Moreover, the switching between the different clock signals may be synchronized to select edges of the low frequency clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.