Vertical integrated photonics chiplet for in-package optical interconnect
US11899251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2020 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | May 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical integrated photonics chiplet assembly includes a package substrate and an external device connected to a top surface of the package substrate. A photonics chip is disposed within the package substrate. The photonics chip includes optical coupling devices positioned at a top surface of the photonics chip. A plurality of conductive via structures are disposed within the package substrate in electrical connection with electrical circuits within the photonics chip. The plurality of conductive via structures are electrically connected through the package substrate to the external device. An opening is formed through the top surface of the substrate to expose a portion of the top surface of the photonics chip at which the optical coupling devices are positioned. An optical fiber array is disposed and secured within the opening such that a plurality of optical fibers of the optical fiber array optically couple to the optical coupling devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.