System and method for timing synchronization
US11899491B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2022 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Oct 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0697
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The system and method generates a pulse or a signal that is transmitted between a central processing unit or processor and an Ethernet integrated circuit card to program a trigger generator in the IC. The pulse is effectively a 1PPS signal that is provided to the IC, which may be in the form a field programmable gate array to enable timing synchronization. The trigger in the IC may also generates an interrupt to the processor so a driver in the CPU is instructed to set the next trigger. For the trigger to be accurately controlled, the control routine is implemented in the driver existing in kernel space rather than user space. A routine or protocol periodically polls the interrupt to determine when the trigger must be reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.