Patent · US Active

Multi-dimensional cache architecture

US11899583B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Joshua Randall · Austin, US
Alejandro Rico Carro · Austin, US
Dam Sunwoo · Austin, US
Saurabh Sinha · Danbury, US
Jamshed Jalal · Austin, US

Key dates

Filing date	Jul 29, 2021
Grant date	Feb 13, 2024
Priority date	—
Expiry date	Jul 29, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH04L49/109
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.