Systolic array-based data processing method and apparatus, medium, and program product
US11899616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2022 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Nov 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a systolic array-based data processing method that includes determining an input splice quantity for the systolic array based on a target input depth and a standard input depth, and determining an output splice quantity for the systolic array based on a target output depth and a standard output depth; inputting the input data matching the input splice quantity to an input buffer of the systolic array in batches, without overlaps in the input data, and processing, by the systolic array, the input data in the input buffer to generate output data corresponding to each piece of input data; and in accordance with a determination that a quantity of output data received by an output buffer of the systolic array from the systolic array matches the output splice quantity, outputting, in the output buffer, output data having a quantity matching the output splice quantity in batches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.