Instructions for fused multiply-add operations with variable precision input operands
US11900107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2022 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Mar 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.