Probabilistic in-memory computing
US11900979B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Nov 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.