Patent · US Active

Shiftable memory and method of operating a shiftable memory

US11901006B2 · kind B2 · utility

0Cited by
7References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 14, 2020
Grant dateFeb 13, 2024
Priority date
Expiry dateOct 30, 2040

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C19/287
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

The present disclosure relates to a shiftable memory comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected, thereby forming chains of memory cells; at least one first serial output data port; output data logic for connecting an output of any of the chains of memory cells to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured for serially collecting serial output data from the output of any of the chains of memory cells; and/or at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any of the chains of memory cells, or at least one parallel input data port and at least one write shift register for serially shifting input data to the input of any of the chains of memory cells; and a controller configured to control the shifting of the data in the chains of memory cells, the controller further configured to control the output data logic and/or the input data logic. The disclosure further relates to a method for operating the shiftable memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.