Semiconductor memory device and method of operating semiconductor memory device
US11901025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2022 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Apr 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.