Manufacturing of cavities
US11901216B2 · kind B2 · utility
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2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Mar 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.