Stress analysis method and semiconductor device manufacturing method
US11901223B2 · kind B2 · utility
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3References
11Claims
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Key dates
| Filing date | Aug 26, 2020 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Aug 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In general, according to one embodiment, a stress analysis method comprising: dividing a surface of an object into a plurality of first rectangles each having a first size, on data; and acquiring a first type value for each of the first rectangles. The method further includes: specifying, from among the first rectangles, a plurality of second rectangles that have the first type value of a magnitude that falls within a first range and form a rectangle; and generating a stress model for a set of the second rectangles by using the second rectangles as an element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.