Chip package method and chip package structure
US11901324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Dec 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Chip package structure is provided. The chip package structure includes: a chip, the chip including metal pins; an organic polymer material layer, the organic polymer material layer being located on a side of the metal pins away from the chip, the organic polymer material layer including a first via hole, and the organic polymer material layer including a first surface away from the chip; metal parts, at least a portion of the metal parts being located in the first via hole, the metal parts and metal pins being electrically connected, the metal parts including a second surface away from the chip, and the second surface and the first surface being flush to each other; and an encapsulating layer, the encapsulating layer being located on a side of the metal parts away from the organic polymer material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.