Semiconductor device
US11901357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Apr 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region, the first active pattern including first source/drain patterns and a first channel pattern between the first source/drain patterns; a second active pattern on the second region, the second active pattern including second source/drain patterns and a second channel pattern between the second source/drain patterns; and a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, wherein a length of the first channel pattern is greater than a length of the second channel pattern, each of the first channel pattern and the second channel pattern includes a plurality of semiconductor patterns stacked on the substrate, and at least two semiconductor patterns of the first channel pattern are bent away from or toward a bottom surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.