Array substrate and method for manufacturing the same, and display apparatus
US11901375B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 13, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Oct 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.