Capacitor architectures in semiconductor devices
US11901404B2 · kind B2 · utility
0Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2022 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Jan 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G11/56
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.