Three-phase inverter power chip and preparation method therefor
US11901840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2020 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Mar 7, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a field of chip technology, and discloses a three-phase inverter power chip and a preparation method therefor. The preparation method includes: forming active areas on a substrate and an isolation area located outside the active areas; forming a source electrode, a drain electrode and a gate electrode of a transistor in each active area; forming a first bond pad, second bond pads, third bond pads and fourth bond pads in the isolation area; the source electrode, the drain electrode and the gate electrode of the chip being extended to the first bond pad, the second bond pads, the third bond pads or the fourth bond pads corresponding thereto; and electrically connecting the source electrode, the drain electrode and the gate electrode of the transistor to the first bond pad, the second bond pads, the third bond pads or the fourth bond pads corresponding thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.