Hybrid fractional-N sampling phase locked loop (PLL) with accurate digital-to-time converter (DTC) calibration
US11901906B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2022 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Aug 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.