Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit of a memory controller
US11901961B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 2022 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Oct 7, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.