Analog-to-digital converter or digital-to-analog converter data path with deterministic latency
US11902132B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 21, 2020 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Feb 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit system includes an analog-to-digital converter circuit, a digital-to-analog converter circuit coupled to the analog-to-digital converter circuit, and a variable latency circuit coupled to a data path that includes the digital-to-analog converter circuit. The variable latency circuit generates a deterministic latency in an output signal that is based on a measured latency of the data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.