Reduction of visual artifacts in parallel video coding
US11902570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2020 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Mar 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/82
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Techniques related to reduction of artifacts in parallel block coding mode selection for video are discussed. Such techniques include, for blocks along a parallel processing split boundary of a video frame, coding mode selection that divides a block into sub-blocks, performs motion estimation for the sub-blocks with skip check disabled and using distortion and coefficient coding cost but exclusive of motion vector coding cost, and evaluates a skip check for the block using the sub-block motion vectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.