Monolithic integration of optical waveguides with metal routing layers
US11906351B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2022 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Sep 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54486
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A photonic integrated circuit and a method for its manufacture are provided. In an embodiment, an intermetal dielectric layer, for example, a silicon oxide layer, is contiguous between an upper metal layer and a lower metal layer on a substrate. One or more waveguides having top and bottom faces are formed in respective waveguide layers within the intermetal dielectric layer between the upper and lower metal layers. There is a distance of at least 600 nm from the upper metal layer to the top face of the uppermost of the several waveguides. There is a distance of at least 600 nm from the lower metal layer to the bottom face of the lowermost of the several waveguides. The waveguides are formed of silicon nitride for longer wavelengths and alumina for shorter wavelengths. These dimensions and materials are favorable for CMOS processing, among other things.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.