Semiconductor strain gage and method of fabrication
US11906375B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2022 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Apr 8, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01L1/205
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure is directed to methods for low-cost, high-volume production of strain gages having substantially uniform gage-to-gage resistances. Strain gages in accordance with the present disclosure are sculpted from a device layer of a semiconductor-on-insulator wafer using deep reactive ion etching, thereby enabling well-controlled electrical properties and physical dimensions of the strain gages. In some embodiments, groups of fully fabricated strain gages are physically connected to handling frames via sprues to facilitate handling, automated assembly, and/or tracing of individual gages from the beginning of fabrication through final packaging. In some embodiments, sprues are configured to mitigate accidental separation of the gages from their frames while simultaneously enabling their removal in response to specific forces applied by a handling tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.