System on a chip and a power down process for IP access resilience
US11907156B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 3, 2021 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Feb 20, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.