Computing system and method of verifying circuit design in computing system
US11907629B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2021 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Jan 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system configured to verify design of an integrated circuit (IC) includes a memory and a processor. The memory is configured to store computer executable instructions. The processor is configured to generate a first coverage model for at least two high-level parameters from the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard or hardware description language (HDL) code by executing the computer executable instructions, generate a second coverage model for low-level internal signals from the HDL code by executing the computer executable instructions, and generate a plurality of test packets for a regression test by using at least one of the first coverage model or the second coverage model by executing the computer executable instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.