High clock-efficiency random number generation system and method
US11907684B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 15, 2022 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Feb 15, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/581
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of generating a series of random number; from a source of random numbers in a computing system. Steps includes: loading a data loop (a looped array of stored values with an index) with random data from a source of random data; then repeating the following: reading a value from the data loop in relation to the index; operating on the multi-bit value thereby outputting a derived random number; and moving the index in relation to the looped array. The data loop may be a simple feedback loop which may be a shift register loaded by direct memory access (DMA). The operation may be performed by one or more arithmetic logic units (ALU) which may be fed by one or more data feeds and may perform XOR, Mask Generator, Data MUX, and/or MOD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.