Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
US11907713B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2019 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Dec 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses relating to a sign modification field for fused operations in a configurable spatial accelerator are described. In one embodiment, a hardware accelerator includes a plurality of processing elements; a network between the plurality of processing elements to transfer values between the plurality of processing elements; and a processing element of the plurality of processing elements comprising: a first plurality of input queues having a multiple bit width coupled to the network, at least one first output queue having the multiple bit width coupled to the network, operation circuitry coupled to the first plurality of input queues having the multiple bit width, a sign modification circuit coupled to the first plurality of input queues having the multiple bit width, and a configuration register within the processing element to store a configuration value comprising a sign modification field that causes the sign modification circuit to modify a sign bit of a value from the first plurality of input queues according to the sign modification field to create a sign modified value, and the configuration value causes the operation circuitry to perform a select…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.