Neural network architecture using control logic determining convolution operation sequence
US11907830B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 5, 2023 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Jan 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware for implementing a Deep Neural Network (DNN) having a convolution layer. A plurality of convolution engines each perform a convolution operation by applying a filter to a data window. Each of the plurality of convolution engines includes multiplication logic that combines a weight of a filter with a respective data value of a data window; control logic that receives configuration information identifying a set of filters for operation on a set of data windows at the plurality of convolution engines; determines a sequence of convolution operations for evaluation at the multiplication logic; requests weights and data values for at least partially applying a filter to a data window; and causes the multiplication logic to combine the weights with their respective data values. Accumulation logic accumulates the results of a plurality of combinations performed by the multiplication logic to form an output for a convolution operation of the determined sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.