Memory device and memory controller and storage device including the memory device and memory controller
US11908535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2021 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Jan 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a memory device and a memory controller, which are configured to repair a weak word line, and a method of operating a storage device including the memory device and the memory controller. A memory device includes a memory cell array including a plurality of normal word lines and at least one spare word line, and a repair controller configured to set memory cells connected to at least one weak word line to a first operation mode and further configured to set memory cells connected to the at least one spare word line to a second operation mode. The at least one weak word line is detected from among the normal word lines based on a test result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.