Integrated circuit device having a bit line and a main insulating spacer with an extended portion
US11908797B2 · kind B2 · utility
0Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2020 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Oct 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.