Planar gate semiconductor device with oxygen-doped Si-layers

US11908904B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Sylvain Leomant · Pörtschach am Wörther See, AT
• Thomas Feil · Villach, AT
• Yulia Polak · Arnoldstein, AT
• Maximilian Roesch · Villach, AT

Key dates

• Filing date: Aug 12, 2021
• Grant date: Feb 20, 2024
• Expiry date: Aug 12, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/60

Abstract

A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.