Electrode structure for vertical group III-V device
US11908905B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 18, 2022 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Jul 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.