Laterally-diffused metal-oxide-semiconductor devices with a multiple-thickness buffer dielectric layer
US11908930B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2021 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Aug 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.