Method and system of dynamically controlling reset signal of IQ divider
US11909407B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Sep 19, 2022 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Sep 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/148
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method to dynamically control a reset signal for an IQ divider are provided. The system includes an IQ divider configured to output a IQ divider output clock; an input configured to receive a reference clock; a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit including an automatic frequency calibration (AFC) logic; and a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.