Semiconductor device and electronic system including the same
US11910603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2021 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Feb 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.