Three-dimensional semiconductor devices
US11910607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2022 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Aug 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
Abstract
A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.