Efficient redundancy management in key-value NAND flash storage
US11914470B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2021 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Jan 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for error correction of logical pages of an erase block of a solid state drive (SSD) memory, the method may include determining an erase block score of the erase block, wherein the calculating is based on a program erase (PE) cycle of the erase block and one or more erase block error correction parameter; determining, based on (a) the erase block score, and (b) a mapping between the erase block score and one or more page error correction parameters for each page type out of multiple pages types, the one or more page error correction parameter for each page type; and allocating, within each page of the erase block, an overprovisioning space and an error correction space, based on at least one page error correction parameter related to a page type of the page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.