Secured boot of a processing unit
US11914718B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 29, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Jun 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.