Side-channel-attack-resistant memory access on embedded central processing units
US11914870B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 4, 2020 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Jun 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure calculate masked data shares dynamically inside the CPU boundary, and use a plurality of memory channels to write the masked data shares to an external memory location and/or to read the data shares from that external memory location. Each dynamically generated mask value is uniquely associated with a corresponding memory channel during writing data to the external memory. The modified masked data is unmasked or remasked during a subsequent read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.