Processing system, related integrated circuit, device and method
US11915008B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 11, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Sep 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30101
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.