Memory devices, circuits and methods of adjusting a sensing current for the memory device
US11915733B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Aug 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.