Resistive memory with enhanced redundancy writing
US11915752B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 31, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | May 12, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.