Nonvolatile memory device and method of detecting wordline defect of the same
US11915773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Aug 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a memory cell array, a voltage generator, a voltage path circuit and a wordline defect detection circuit. The memory cell array includes memory cells and wordlines connected to the memory cells. The voltage generator generates a wordline voltage applied to the wordlines. The voltage path circuit between the voltage generator and the memory cell array transfers the wordline voltage to the wordlines. The wordline defect detection circuit is connected to a measurement node between the voltage generator and the voltage path circuit. The wordline defect detection circuit measures a path leakage current of the voltage path circuit based on a measurement voltage of the measurement node to generate an offset value corresponding to the path leakage current in a compensation mode and determines defect of each wordline of the wordlines based on the offset value and the measurement voltage in a defect detection mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.