Manufacturing method of semiconductor structure
US11915933B2 · kind B2 · utility
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Key dates
| Filing date | Aug 17, 2021 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Oct 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31058
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a semiconductor structure is disclosed, which includes: an initial structure is provided; a filling layer covering a spacer is formed on the initial structure; a filling layer with a first preset thickness is removed at a high first etching rate through a first etching process, then a filling layer with a second preset thickness is removed at a low second etching rate through a second etching process, and the partial spacer is exposed; and the filling layer and the spacer are patterned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.