DDR phy parallel clock paths architecture

US11916558B1 · kind B1 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Yong Xu · Brooklyn, US
• Boris Andreev · San Diego, US
• Vikas MAHENDIYAN · San Diego, US
• Yuxin Li · Freeport, US
• Anand Meruva · San Diego, US
• Jeffrey Mark Hinrichs · San Diego, US

Key dates

• Filing date: Dec 13, 2022
• Grant date: Feb 27, 2024
• Expiry date: Dec 13, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/22
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.