Power efficiency in an analog feedback class D modulator
US11916707B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 23, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | May 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for architectures for an analog feedback class D modulator that increase the power efficiency of the class D modulator. In particular, systems and methods are provided for an analog feedback class D modulator having a digital feed-forward loop. The digital feed-forward loop allows for removal of signal content from an input to an analog-to-digital converter, such that the ADC processes just noise and/or error. Using the techniques discussed herein, the loop filter is low power as it processes error content but not signal content.
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