Driver device layouts
US11917734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2023 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Mar 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B45/40
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An example circuit includes a substrate having a plurality of scan lines substantially orthogonal to a virtual centerline of the substrate. The circuit also includes a first driver integrated circuit (IC) on the substrate, the first driver IC including: a set of line switches coupled to a first set of the plurality of scan lines along a side of the first driver IC nearest the virtual centerline; a data output and a register. The circuit also includes a second driver IC on the substrate, the second driver IC including: a set of line switches coupled to a second set of the plurality of scan lines along a side of the second IC nearest the virtual centerline; and a data input coupled to the data output of the first driver IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.