Method of manufacturing semiconductor structure and semiconductor structure
US11917806B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2021 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Nov 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.