Method and apparatus for dual multiplication units in a data path
US11921643B2 · kind B2 · utility
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11References
20Claims
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Key dates
| Filing date | Mar 9, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Mar 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2017/0298
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.