Patent · US Active

Scalable bandwidth efficient graph processing on field programmable gate arrays

US11921786B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

SAP SE · DE

Inventors

Jonas Dann · Heidelberg, DE
Daniel Ritter · Heidelberg, DE

Key dates

Filing date	May 18, 2022
Grant date	Mar 5, 2024
Priority date	—
Expiry date	Jul 8, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F16/9024
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for graph processing in a scalable graph processing framework may include applying a two-dimensional partitioning scheme to partition a graph. One or more partitions of the graph may be distributed to each graph core such that each graph core executes a graph processing algorithm on one or more partitions of the graph. The executing of the graph processing algorithm may include the graph cores exchanging vertex labels via a crossbar interconnecting the plurality of graph cores. Each graph core in the scalable graph processing framework may be coupled with a single memory channel upon which the partitions of the graph are distributed.The graph cores may synthesized on a field programmable gate array (FPGA) based on one or more user defined functions (UDFs). Related systems and computer program products are also provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.